1. Field of the Invention
The present invention relates to a multilevel metallization and a method for forming the same, and more specifically to an improved pillar structure for interconnection between two different levels of wiring conductors, and a method for forming the improved pillar connection.
2. Description of Related Art
In the prior art, a vertical connection between two different levels of wiring conductors in a multilevel metallization has been effected by completely charging a conducting material into a through hole or via hole formed in an interlayer insulating layer, by vacuum evaporation or by sputtering. However, an advanced integrated circuit technology, particularly, an increased integration density of the integrated circuit has made it difficult to realize a stable interlayer interconnection by means of through holes. In order to overcome this problem, it has been proposed to previously form a stud-like connection member, often called a "pillar", on a lower level metallization so as to vertically protrude from the lower level metallization, whereby a good interlayer connection between the lower level metallization and an upper level metallization can be realized by the conductive pillar vertically protruding from the lower level metallization.
Referring to FIGS. 1 and 2, there is diagrammatically shown a typical example of a conventional conductive pillar vertically protruding from the lower level metallization. As shown in FIG. 1, a plurality of lower level conductors 12 are formed on a semiconductor substrate 10, and a conductive pillar 14 is formed on the lower level conductor 12 at a pillar connection portion 16 where a through hole 18 is to be formed in an interlayer insulator (not shown) which is to be formed to cover the lower level conductors 12 for the purpose of interconnection between the lower level conductors 12 and an upper level conductor (not shown) to be formed on the interlayer insulator. As seen from FIG. 2, however, in order to previously ensure a tolerance of alignment and to compensate for variation of dimensional accuracy in the semiconductor process, it has been necessary to widen the portion 16 of the lower level conductor 12 where the pillar 14 is formed with the result that a conductor pattern pitch (line pitch) must be enlarged. For example, assuming that a width of each conductor 12 is "F" at a portion excluding the pillar connection portion 16 and "2F" at the pillar connection portion 16, and that a minimum space between each pair of adjacent conductors is "F", the conductor pattern pitch must be "3F". In other words, it is disadvantageous in that the wiring density has been decreased.
Recently, K. Haberle et al. proposed has, in Proceedings of IEEE V-MIC Conference, 1988, pp117-124, that the wiring conductors and the pillars are formed of gold metallization so as to reduce the wiring pitch. Referring to FIGS. 3 and 4, there is diagrammatically shown a conductive pillar proposed by K. Haberle et al. As shown in FIG. 4, a through hole 18A is formed to have a size larger than the width of the lower level conductor 12 formed on the substrate 10, and then, as shown in FIG. 3, a pillar 14A is formed to straddle the lower level conductor 12 by means of a gold plating method.
In this method, assuming that the width of each lower level conductor 12 is "F" and the width of the pillar 14A is "2F" in a direction perpendicular to the longitudinal direction of the lower level conductor 12, the wiring pitch (line pitch) can be made "2.5F", which is shorter than the example shown in FIGS. 1 and 2. However, due to possible misalignment of mask patterns and due to variations of the shape of the pillar, there is an danger of short-circuiting between adjacent conductors or another danger of increasing a wiring capacitance even if the adjacent conductors are not short-circuited. In other words, in order to avoid these dangers, the wiring pitch (line pitch) cannot be sufficiently reduced.